A CMOS imager circuit includes a focal plane array of pixel cells. Each one of the pixel cells includes a photosensor, which may be a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and typically includes an output field effect transistor formed in the substrate and a charge transfer section, typically a floating diffusion node, formed on the substrate adjacent the photosensor connected to the gate of the output transistor.
The active elements of an individual pixel cell in a CMOS imager circuit perform a number of functions, including: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge is typically converted to a pixel output voltage by a source follower output transistor.
FIG. 1 is a top plan view of a typical CMOS imager pixel cell 10. FIG. 2 is a schematic diagram of the CMOS imager pixel of FIG. 1. As is known in the art, a pixel cell receives photons of light and converts those photons into charge carried by electrons. To perform this function, each pixel cell 10 includes a photosensor 20. The photosensor, which can be a photogate, photoconductor, pinned photodiode, or other photosensitive device, includes a charge accumulation region 30 which accumulates electrons produced by photons of light.
Each pixel cell also includes a transfer transistor 40 for transferring charge from the charge accumulation region 30 to a floating diffusion region 50, and a reset transistor 60 for resetting the floating diffusion region 50 to a predetermined charge level, VAA-PIX, prior to charge transfer. The pixel cell 10 also may include a source follower transistor 70 for receiving and amplifying a charge level from the diffusion region 50 and a row select transistor 80 for controlling the readout of the pixel cell 10 contents from the source follower transistor 70. The reset transistor 60, source follower transistor 70, and row select transistor 80 include source/drain regions 120, 130, and 140. There is also a contact to the gate of the source follower transistor 70.
Each pixel cell includes several contacts, such as 90, 100, and 110, to provide electrical connections for the pixel cell 10. For example, in the embodiment shown in FIG. 1, a source/drain region of the reset transistor 60 is electrically connected to an array voltage source terminal (VAA-PIX) through contact 100, the gate of the source follower transistor 70 is connected to the floating diffusion region 50 through contact 90, and an output voltage VOUT is output from the pixel cell 10 through contact 110.
FIG. 3 illustrates a block diagram of a CMOS imager circuit 190 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of rows and columns. A plurality of row and column lines are provided for the entire array 200, selectively activated by the row driver 210 in response to row address decoder 220 and the column driver 260 in response to the column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager circuit 190 is operated by the control circuit 250, which controls address decoders 220 and 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210 and 260, which apply driving voltage to the drive transistors of the selected row and column lines.
CMOS imager pixels cells and circuits of the type described above are generally known as discussed, for example, in the U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A problem that causes error in CMOS imager circuit output is the injection of unwanted charges into the data path. In a CMOS imager pixel, there are several common sources of charge injection, including charge-to-voltage conversion error charges, redistribution of transistor channel charges after the transistors are switched off, and redistribution of charges accumulated by charge coupling from the reset transistor 60 gate-source overlap capacitor COVL. Charge injection will introduce an unknown amount of “noise” charge into the floating diffusion region 50, decreasing the accuracy of the output signal VOUT. This problem is commonly addressed by using a correlated double sampling (CDS) technique to subtract the noise value from the signal, as described below.
FIG. 4 shows a timing diagram of a typical CMOS imager circuit performing CDS. In performing CDS, generally, first a reset pulse RST is applied to the gate of the reset transistor 60, turning on the transistor 60 and charging the floating diffusion region 50 to VAA-PIX less the voltage drop VTH of the transistor 60. Accordingly, the floating diffusion region is set to a known reference value VAA-PIX-VTH. The charge on the floating diffusion region 50 is applied to the gate of the source follower transistor 70 to control the current passing through the row select transistor 80. Upon the pulse of a signal SHR, a voltage based on the current is stored by sample and hold circuit 265. After the floating diffusion region 50 has been set and the reference voltage stored, charge collected in the charge accumulation region 30 by the photosensor 20 is transferred from the charge accumulation region 30 to the floating diffusion region 50 by the pulse of a signal TX to the gate of the transfer transistor 40. Upon the pulse of a signal SHS, the new output charge in the floating diffusion region 50 is translated to an output voltage that is stored in the sample and hold circuit 265. As shown in FIG. 3, the sample and hold circuit outputs two signals, corresponding to the stored sampled vales of the reference value Vrst and the photosensor accumulated charge value Vsig. These two signals are subtracted by a differential amplifier 267 to produce the signal Vrst-Vsig, which represents the amount of light impinging on the pixel less certain unwanted noise charges. This difference signal is digitized by an analog to digital converter 275. The digitized pixel signals are then fed to an image processor 280 to form a digital image.
However, not all unwanted charge injection can be subtracted out using CDS. Some of the active elements of CDS may be a source of charge injection themselves. Particularly, as the reset transistor 60 is not an ideal switch, when it turns off some portion of the channel charges will relocate to the floating diffusion region 50. CDS can also cause other problems by reducing the available voltage swing on the floating diffusion region 50, thereby increasing lag and reducing the dynamic range of the pixel output signal Vsig. This problem is expected to get worse as developments trend to the scaling of the floating diffusion region 50 area to achieve higher conversion gain.
Accordingly, it would be advantageous to have an improved image sensor to help suppress charge injection without contributing to lag or reducing the available voltage swing on the floating diffusion region.